`define IDLE 16'd0;
`define AND_R0_R7_0 16'b0101_000_111_1_00000;
module ram #(
	parameter DATA_SIZE = 16,
	parameter ADDR_SIZE = 16
) (
	input [DATA_SIZE-1:0]DATA_IN,
	input WE,//写/读使能信号，WE=0为读操作；WE=1为写操作
	input [ADDR_SIZE-1:0]ADDRESS,
	output reg[DATA_SIZE-1:0]DATA_OUT
);
localparam MEM_DEPTH=1<<ADDR_SIZE;

	reg [DATA_SIZE-1:0]MEM[0:MEM_DEPTH-1];

	always @(WE or DATA_IN or ADDRESS) begin
		if(WE==1'b1) begin
		MEM[ADDRESS] = DATA_IN;
		end
		else 
		  	case(ADDRESS)
			  //Initialize
			//16'b0000000000000000:
			16'd0:
				begin
				DATA_OUT = 16'b0101_000_111_1_00000;$display("\n At time %0t :  AND R0:(DR) R7:(SR1) 0:(imm5)  => R0=0 ",$time);end 
				// AND R0 R7 0  => R0=0
			16'd1: 
			  	begin
				DATA_OUT = 16'b0101_001_111_1_00000;$display("\n At time %0t : AND R1 R7 0 => R1=0 ",$time);end
				//AND R1 R7 0 =>R1=0
			16'd2:
				begin
				DATA_OUT = 16'b0101_010_111_1_00000;$display("\n At time %0t : AND R2 R7 0 => R2=0",$time); end
				//AND R2 R7 0 =>R2=0
			16'd3:
				begin
				DATA_OUT = 16'b0101_011_111_1_00000;$display("\n At time %0t : AND R3 R7 0 => R3=0",$time); end
				//AND R3 R7 0 =>R3=0
			16'd4:
				begin
				DATA_OUT = 16'b0101_100_111_1_00000;$display("\n At time %0t : AND R4 R7 0 => R4=0",$time); end
				//AND R4 R7 0 =>R4=0
			16'd5:
				begin
				DATA_OUT = 16'b0101_101_111_1_00000;$display("\n At time %0t : AND R5 R7 0 => R5=0",$time); end
				//AND R5 R7 0 =>R5=0
			16'd6:
				begin
				DATA_OUT = 16'b0101_110_111_1_00000;$display("\n At time %0t : AND R6 R7 0 => R2=0",$time); end
				//AND R6 R7 0 =>R6=0
			16'd7:
				begin
				DATA_OUT = 16'b0101_111_111_1_00000;$display("\n At time %0t : AND R7 R7 0 => R7=0\n Initialize Finished!!!",$time); end
				//AND R7 R7 0 =>R7=0
			  //Test_ADD
			16'd8:
				begin	
				DATA_OUT = 16'b0001_001_000_1_00010;$display("\n At time %0t : ADD R1 R0 imme:010=2 => R1=2",$time); end
			16'd9:
				begin
				DATA_OUT = 16'b0001_010_000_1_00101;$display("\n At time %0t : AND R2 R0 imme:101 => R2=5",$time); end
				//AND R7 R7 0 =>R7=0
			16'd10:
				begin	
				DATA_OUT = 16'b0010_000_000000010;$display("\n At time %0t : LD R0 PCoffset9:2 => PC+2=PC`",$time);
				end
			16'd12:
				begin
					DATA_OUT = 16'b0000_000_000000001;$display("\n At time %0t :  R0 <= 16'b0000_000_000000001",$time);		
				end
			16'd13:
				begin
					$finish;
				end
			default:  DATA_OUT = DATA_OUT; 
			endcase
		end
endmodule